<>VHDL Write a two digit numeric comparator

The two digit value comparator is a comparator composed of four inputs and three outputs , Realize the comparison of the size of two binary numbers （ High and low levels are used to represent input and output ） The truth table is as follows ：

（xx Table arbitrary state ）
Therefore, when designing , definition 4 Multiple inputs and 3 Entities at multiple outputs , Respectively A1A0,B1B0 and f1(a>b)f2(a<b)f3(a=b)
The specific codes are as follows ：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY homework2 IS PORT(A1:IN
STD_LOGIC; -- definition 4 Multiple inputs and 3 Multiple outputs A0:IN STD_LOGIC; B1:IN STD_LOGIC; B0:IN STD_LOGIC;
f1:OUT STD_LOGIC; f2:OUT STD_LOGIC; f3:OUT STD_LOGIC); END homework2;
ARCHITECTURE HA OF homework2 IS SIGNAL tmp:STD_LOGIC_VECTOR(3 DOWNTO
0);-- Define a signal array BEGIN tmp<=A1 & B1 & A0 & B0; -- use & Connect four input values , And assign to tmp PROCESS(tmp)
BEGIN CASE tmp IS --CASE Statement implementation specific code WHEN "0000" =>f1<='0';f2<='0';f3<='1'; WHEN
"0001" =>f1<='0';f2<='1';f3<='0'; WHEN "0010" =>f1<='1';f2<='0';f3<='0'; WHEN
"0011" =>f1<='0';f2<='0';f3<='1'; WHEN "0100" =>f1<='0';f2<='1';f3<='0'; WHEN
"0101" =>f1<='0';f2<='1';f3<='0'; WHEN "0110" =>f1<='0';f2<='1';f3<='0'; WHEN
"0111" =>f1<='0';f2<='1';f3<='0'; WHEN "1000" =>f1<='1';f2<='0';f3<='0'; WHEN
"1001" =>f1<='1';f2<='0';f3<='0'; WHEN "1010" =>f1<='1';f2<='0';f3<='0'; WHEN
"1011" =>f1<='1';f2<='0';f3<='0'; WHEN "1100" =>f1<='0';f2<='0';f3<='1'; WHEN
"1101" =>f1<='0';f2<='1';f3<='0'; WHEN "1110" =>f1<='1';f2<='0';f3<='0'; WHEN
"1111" =>f1<='0';f2<='0';f3<='1'; END CASE; END PROCESS; END HA;
The simulation results are as follows ：

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