Bus overview

               
Bus : A group of common information transmission lines that can share time for multiple components . Sharing means that multiple components can be attached to the bus , The information exchanged between the various components can be transmitted through this group of common lines ; Time sharing means that only one component can transmit information on the bus at the same time .

                Classification of bus :

                            Classification by function

                                     
 1> On chip bus : Bus in chip , It is CPU Between registers in chip , Register and ALU Public connection between       Line .  The on-chip bus is inside the chip , It's usually invisible .

                                       
2> system bus : Functional components in computer system (CPU, Main memory ,I/O Interface ) The buses are connected to each other , The system bus is also known as the internal bus    
Line , Is the main component of the computer . System bus can be divided into data bus according to different information , Address bus and control bus .

                                       
3> Communication bus ( External bus ): Used between computer systems or between computer systems and other systems ( Telecommunication equipment , Test equipment ) Information between     Transmitted bus .

                            Sort by number of data lines

                                       
1> Parallel bus : A bus with multiple bidirectional data lines , It can realize multi bit simultaneous transmission of a data . Parallel bus has data transmission  
Advantages of high rate , However, the transmission characteristics of each data line cannot be completely consistent , When the data line is long , The delay of data bits arriving at the receiving end may be inconsistent , Will cause transmission error .

                                     
 2> Serial bus : A bus with only one bidirectional or two unidirectional data lines , Serial bus can realize a data bit according to one  
Fixed speed and sequence transmission . Because the serial transmission of data by bit does not require high transmission characteristics of data line , In the case of long-distance connection, data can still be effectively transmitted , So the advantage of serial bus is long distance communication .

              Bus structure :

                          Single bus structure : There is only one system bus , All components are connected through the system bus .

                          

                            Dual bus structure : On the basis of single bus structure, a dedicated CPU The data transfer path between and main memory .

                            

                         

                          Three bus structure : Add another one on the basis of dual bus I/O Bus .

                          

                Performance index of bus :   

                          1> Bus width : Refers to the number of lines in the bus , It determines the physical space and cost of the bus . The most direct impact on bus width is the address line and data  
  Number of lines , The width of the address line indicates the address space range of the memory that the bus can directly access , The width of the data indicates the number of bits of data that can be exchanged when accessing a memory or peripheral device .

                          2> Bus bandwidth : Maximum transfer rate of the bus , This is the number of bytes transferred per second .

                          3> Bus load : Refers to the maximum number of devices connected to the bus . The load capacity of most buses is limited .

                         
4> Bus multiplexing : The same signal line on the bus is used to transmit different signals in different time periods , For example, the address bus and the data bus share a set of signal lines . The purpose of this approach is to reduce the number of buses , Improve bus utilization .

                          5> Bus burst transmission : In a bus cycle, multiple data with consecutive storage addresses can be transmitted .

           

              Bus arbitration :
The bus control mechanism is equipped with bus optimization and arbitration control logic , That is, according to a certain priority to determine which component first uses the bus , Only components that have access to the bus , To start data transfer .

                        Chain query mode :

     

                       
 I/O Interface through BR Request to bus , Only in BS Before the signal is established ,BR Can be responded by the bus controller , And send it out BG Answer the signal .BG The signal passes through each component in series , If a part itself has no bus request , The signal is passed on to the next component , Until the corresponding part is found . According to the priority of query mode , In the query chain, the device closer to the bus controller has the highest priority .

            Counter timing query mode :

               
The bus is receiving BR After request , stay BS by 0 In the case of , Let the counter start counting , Periodically query each component to determine who made the request . When the count value on the query line is consistent with the part number of the request , This component makes BS Set as 1, Access to the bus . This counting can be done from 0 start , You can also start at the midpoint . The initial value of the counter can be set by the program , Increase the flexibility of the system .

            Independent request mode :     

                       
  Each component sharing the bus has a pair of control wires . When a part requests to use the bus , It will be sent out BR, There is a queuing circuit in the bus controller , According to a certain priority, it determines which part to respond to the request first .

 

      Bus timing control :

               
  Synchronous timing mode : The system uses a unified clock signal to coordinate the transmission timing relationship between the sender and the receiver . Clocks produce equal time intervals , Each time interval constitutes a bus cycle . In a bus cycle , The sender and receiver can transmit data once . Because the operation is carried out within the specified time period , therefore , The sender does not have to wait for the receiver to respond , When this period is over , Automatically proceed to the next operation . The clock frequency in the synchronous mode must be able to meet the needs of the longest delay and slowest interface on the bus , So the efficiency is low ; It is also impossible to know whether the visited peripheral is responding , So the reliability is low .

               
Asynchronous timing mode : There is no fixed time interval , Depending on the transmission, both sides restrict each other " handshake " Signal to achieve timing control . The main equipment proposes to exchange information " request " signal , Through the interface to the slave device , Then it happens from the slave device to the master device " answer " signal ." request " reach " answer " Is determined by the actual time of the operating system , It has strong flexibility . Asynchronous control can ensure the reliable exchange of information between two parts or equipment with great difference in working speed , Automatic completion time coordination , But the control is more complex than the synchronous mode , The cost will also be higher .

                      Asynchronous according to " request " and " answer " Whether interlocking is divided into 3 Situation in China :

                         1. Non interlock :" request " and " answer " All signals have a certain time width ," request " The end of the signal and " answer " The end of the signal is not interlocked .

                         2. Semi interlock :" request " The cancellation of the signal depends on the response received " signal ", and " answer " The cancellation of the signal depends on the device .

                         3." request " The cancellation of the signal depends on " answer " The arrival of the signal , and " request " The cancellation of the signal leads to an answer " signal " Revocation of .

     

      External bus : A bus connecting computer systems , Standard interface plug is usually used , Its structure and communication protocol are also standard .

               1. Serial port and parallel port

                   
1> Serial port : Also known as communication port and COM mouth , It is mainly used for equipment that needs two-way communication with the system . The traditional serial port is asynchronous transmission , And oriented characters . Each character sent over a serial connection is formed by a standard start stop signal , Each character is preceded by a separate binary "0"( Start bit ), Subsequent 8 Binary numbers will make up a byte of data , There are 1 Or 2 Binary "1"( Stop bit ). At the receiving end of communication , Character recognition is based on the start stop signal .

                   2> Parallel port : Yes 8 Data lines , You can transfer data through this 8 Data lines occur at the same time, containing all units of one byte of data .

             2.USB Interface : A peripheral bus standard , With plug and play function .USB A dedicated port is no longer needed , It's also down I/O Use of cards , It greatly reduces important system resources .

 

 

reference material :<< Principles of Computer Organization >> Jiang Benshan

                

 

 

                                 

 

 

Technology
©2020 ioDraw All rights reserved
C++ Super God welcome Microsoft as father : Please write the game code again realization LRU Cache(java edition )( Essence )2020 year 6 month 26 day C# Class library Ip Address help class Wechat applet instant chat dialog window static source code django Do not close CSRF middleware , Custom through CSRF Tested post request Advanced programmer - Deep understanding of data structure Enterprises face SEM Bidding and SEO How to choose ? Or both ?3. backward analysis Hello World! program - lower Vue2.0+jsonserver+axios Simulate local request interface data HashMap realization LRU( Least recently used ) Cache update algorithm