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one , brief introduction
* PLL（Phase-locked loop） Phase locked loop . yes FPGA Important resources in . Because of a complex FPGA
Systems often require multiple different frequencies , Phase clock signal . therefore , One FPGA In chip PLL The number of is measured FPGA Important indicators of chip capability .FPGA In the design of , Clock system
FPGA High speed design is extremely important , A low jitter , The system clock with low delay will increase FPGA Design success rate .
* Digital phase locked loop （PLL）： It is mainly used for frequency synthesis . Use one PLL Multiple clocks can be generated from one input clock signal
signal .
* List item
two ,PLL IP Core call
with Vivado Software operation as an example
1, Create a new one engineering , click Project Manager Under the interface IP Catalog.
2, stay IP Catalog Search in clock, Open the following Clocking Wizard, Double click to open the configuration interface .
Configuration interface
3, Clocking Wizard Your name can be modified , I don't make any changes here . In the first interface Clocking Options in , We choose PLL
resources , The input clock frequency is 50Mhz.
4, stay Output Clocks Select clock output in the interface , Here I choose clk_out1~clk_out4 Output of four clocks , The frequencies are 100Mhz,
75Mhz, 50Mhz, 25Mhz. The phase of the clock output can also be set here , We don't make settings , Keep default phase , click OK complete ,（ We can preview it on the left ）
5, Click in the pop-up dialog box Generate Button generation PLL IP Design documents .
6, Then one clk_wiz_0.xci of IP Will be automatically added to our In the project , You can double-click it to modify this IP Configuration of
choice IP Sources This page , Then double-click to open it clk_wiz_0.veo file , This is provided in this document IP
Instantiation template for . We just need to copy the contents of the box to us verilog In the program , yes IP Instantiate .
7, Next, create a new top-level file , And will pll Instantiate template copy go in , Make some changes
The code is as follows ：
`timescale 1ns / 1ps module pll_test( input sys_clk, //system clock 50Mhz on
board input rst_n, //reset ,low active output clk_out_100M, //pll clock output
output clk_out_75M, //pll clock output output clk_out_50M, //pll clock output
output clk_out_25M//pll clock output ); wire locked; /PLL IP call clk_wiz_0
clk_wiz_0_inst (// Clock in ports .clk_in1(sys_clk), // IN 50Mhz // Clock out
ports .clk_out1(clk_out_100M), // OUT 200Mhz .clk_out2(clk_out_75M), // OUT
100Mhz .clk_out3(clk_out_50M), // OUT 50Mhz .clk_out4(clk_out_25M), // OUT 25Mhz
// Status and control signals .reset(~rst_n), // pll reset, high-active .locked(
locked)); // OUT endmodule
The simulation files are as follows ：
`timescale 1ns / 1ps // // Module Name: vtf_led_test // module vtf_pll_test;
// Inputs reg sys_clk; reg rst_n; // Outputs wire clk_out; // Instantiate the
Unit Under Test (UUT) pll_test uut ( .sys_clk(sys_clk), //system clock 50Mhz on
board .rst_n(rst_n), //reset ,low active .clk_out_100M(clk_out_100M), //pll
clock output .clk_out_75M(clk_out_75M), //pll clock output .clk_out_50M(
clk_out_50M), //pll clock output .clk_out_25M(clk_out_25M) //pll clock output );
initial begin// Initialize Inputs sys_clk = 0; rst_n = 0; // Wait 100 ns for
global reset to finish #100; rst_n = 1; // Add stimulus here #20000; // $stop;
end always #10 sys_clk = ~ sys_clk; //5ns One cycle , produce 50MHz Clock source endmodule
simulation
result ：
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