module divid( input clk, input rst_n, input [15:0] din, output reg [1:0]
y_dout, output reg[15:0] s_dout ); reg [15:0] temp_data; reg end_flag; always @
(posedge clk or negedge rst_n) begin if(!rst_n) begin temp_data <= din; end else
begin temp_data<= temp_data - 2'd3; end end always @ (posedge clk or negedge
rst_n) begin if(!rst_n) begin end_flag <= 1'b0; end else if(temp_data <= 2'd3)
begin end_flag <= 1'b1; end else begin end_flag <= 1'b0; end end reg [15:0]
cnt; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin cnt <= 16'd0
; end else if(end_flag) begin cnt <= 16'd0; end else begin cnt <= cnt + 1'b1;
end end always @(posedge clk or negedge rst_n) begin if(!rst_n) begin y_dout <=
2'd0; end else if(temp_data <= 2'd3) begin y_dout <= temp_data[1:0]; end end
always @(posedge clk or negedge rst_n) begin if(!rst_n) begin s_dout <= 16'd0;
end else if(temp_data <= 2'd3) begin s_dout <= cnt; end end endmodule

=
1’b1插入到原序列最高位；遇到101，则插入2’b10,遇到11，不做操作。在实际写代码的时候，将被除数一位一位从高到低输入进来，可以把商每次左移一位，这样做完整个序列以后最开始计算出来的商的位就到了高位上，避免了使用寄存器索引。

module divide_by_three #( parameter DATAWIDTH = 16 )( input clk, input rst_n,
input vld_in, input[DATAWIDTH-1:0] data_in, output reg [DATAWIDTH-1:0]
quotient, output reg[1:0] reminder, output reg vld_out ); reg [1:0] c_state; reg
[1:0] n_state; reg [\$clog2(DATAWIDTH):0] cnt; reg [DATAWIDTH-1:0] data_reg;
parameter IDLE= 2'b11; always @ (posedge clk or negedge rst_n) begin if(!rst_n)
begin c_state <= IDLE; end else begin c_state <= n_state; end end always @ (*)
begin case(c_state) IDLE : if(vld_in) n_state = 2'b00; else n_state = IDLE; 2
'b00 : if(cnt==DATAWIDTH) n_state = IDLE; else if(data_reg[DATAWIDTH-1])
n_state = 2'b01; else n_state = 2'b00; 2'b01 : if(cnt==DATAWIDTH) n_state = IDLE
; else if(data_reg[DATAWIDTH-1]) n_state = 2'b00; else n_state = 2'b10; 2'b10 :
if(cnt==DATAWIDTH) n_state = IDLE; else if(data_reg[DATAWIDTH-1]) n_state = 2'
b10; else n_state = 2'b01; default : n_state = IDLE; endcase end always @
(posedge clk or negedge rst_n) begin if(!rst_n) begin
{cnt,data_reg,reminder,quotient,vld_out} <= 0; end else begin case(c_state)
IDLE : begin {vld_out,cnt} <= 0; if(vld_in) begin data_reg <= data_in; end else
begin data_reg <= data_reg; end end 2'b00,2'b01,2'b10 : begin if(cnt==
DATAWIDTH-1) begin cnt <= cnt + 1; reminder <= n_state; vld_out <= 1; end else
begin cnt<= cnt + 1; vld_out <= 0; data_reg <= {data_reg[DATAWIDTH-2:0],1'b0};
end if(data_reg[DATAWIDTH-1]) begin quotient <= {quotient[DATAWIDTH-2:0],c_state
[1]|c_state[0]}; end else begin quotient <= {quotient[DATAWIDTH-2:0],c_state[1]}
; end end endcase end end endmodule

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