<>VHDL实现全加器

1.一位全加器

F=A⊕B⊕Ci
Co=Ci(A⊕B)+AB

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED; ENTITY
homework5 IS PORT( a,b,ci:IN STD_LOGIC; f,co:OUT STD_LOGIC ); END homework5;
ARCHITECTURE yejiayu OF homework5 IS BEGIN f<=(a XOR b)XOR ci; --F=A⊕B⊕Ci
co<=((a XOR b)AND ci)OR(a AND b); --Co=Ci(A⊕B)+AB END yejiayu;

2.四位全加器

（1）元件例化方法实现：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY homework6 IS PORT( A0,A1,A2,A3,B0,B1,B2,B3:IN STD_LOGIC; F0,F1,F2,F3:OUT
STD_LOGIC; CI:IN STD_LOGIC; CO:OUT STD_LOGIC ); END homework6; ARCHITECTURE
yejiayu OF homework6 IS COMPONENT homework5 --COMPONENT语句来实现元件例化方法 PORT(
a,b,ci:IN STD_LOGIC; f,co:OUT STD_LOGIC ); END COMPONENT homework5; SIGNAL
S0,S1,S2:STD_LOGIC; BEGIN U1:homework5 port map(A0,B0,CI,F0,S0); U2:homework5
port map(A1,B1,S0,F1,S1); U3:homework5 port map(A2,B2,S1,F2,S2); U4:homework5
port map(A3,B3,S2,F3,CO); END yejiayu;

（接下来注意！！！）

（2）简化实现四位全加器

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY homework7 IS PORT( A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); F:OUT
STD_LOGIC_VECTOR(4 DOWNTO 0)); END homework7; ARCHITECTURE yejiayu OF homework7
IS BEGIN PROCESS(A,B) BEGIN F<="00000"+A+B; END PROCESS; END yejiayu;

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